1. Field of the Invention
The present invention relates to a data processing system and a slave device. More particularly, the present invention relates to a data processing system in which a master device which issues a data transmission request and a slave device which performs data transmission in response to the request are connected to each other via a system bus, and to the slave device.
2. Description of the Background Art
A conventional data processing system in which data request and transmission are performed between a master device and a slave device is generally realized with a configuration such as that shown in FIG. 12. In the conventional data processing system shown in FIG. 12, a master device 500 and a slave device 100 are connected to each other via a system bus 600. The slave device 100 includes a bus interface 101, a data buffer 102, a prefetch control section 103, and a memory 105.
When the master device 500 needs data held by the slave device 100, the master device 500 transmits to the slave device 100 a read transfer request for the data. The slave device 100 having received the read transfer request from the master device 500 then temporarily stores in the data buffer 102 contiguous data units starting at an associated address in the memory 105, for a subsequent burst transfer.
In a normal DMA transfer, the master device 500 presets in the slave device 100 information such as the number of words to be transferred. By doing so, the slave device 100 can read data of only the necessary number of words from the memory 105 and temporarily store the data in the data buffer 102. In a bus protocol such as a PCI bus, however, the slave device 100 starts on a prefetching process of data upon reception of a first request from the master device 500, and responds to a request for reception after the prefetching process of the data has been completed. Here, even if the number of words for a read transfer requested by the master device 500 to the slave device 100 is one word, since the slave device 100 does not know the requested number of words for the read transfer, the slave device 100 reads contiguous data units having a quantity equal to the number of stages in the data buffer 102 from the memory 105 and then temporarily stores the contiguous data units in the data buffer 102. Therefore, in a system in which a burst transfer does not occur or a system in which only such a burst transfer occurs that the number of data units to be transferred is smaller than the number of stages in the data buffer 102 of the slave device 100, unnecessary data transfer is caused in the slave device 100, resulting in inefficient data transfer in the entire system. FIG. 13 is a diagram for describing data processing for the case where the number of prefetch words is “8” and the number of data units requested by the master device 500 is “1”.
As techniques for solving the above-described problem, there is suggested a technique for improving the utilization efficiency of the system bus by optimizing the quantity of data to be transferred according to the maximum buffer size of the slave device 100. See, for example, Japanese Laid-Open Patent Publication No. 2000-330929.
In a slave device of the above-described conventional technique, however, although a data write transfer from a master device to the slave device is considered, a data read transfer from the slave device to the master device is not considered.